Structures and methods for forming high density trench field effect transistors

ABSTRACT

A semiconductor structure comprises trenches extending into a semiconductor region. Portions of the semiconductor region extend between adjacent trenches forming mesa regions. A gate electrode is in each trench. Well regions of a first conductivity type extend in the semiconductor region between adjacent trenches. Source regions of a second conductivity type are in the well regions. Heavy body regions of the first conductivity type are in the well regions. The source regions and the heavy body regions are adjacent trench sidewalls, and the heavy body regions extend over the source regions along the trench sidewalls to a top surface of the mesa regions.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/211,654, filed Sep. 16, 2008, entitled “High Density Trench FieldEffect Transistor”, which is incorporated by reference herein in itsentirety.

BACKGROUND

The present invention relates in general to semiconductor technology,and more particularly, to structures and methods for formingsemiconductor devices in shielded and non-shielded gate trench fieldeffect transistors (FETs) with minimum cell pitch.

To increase transistor packing density of trench FETs, it is desirableto minimize the trench width as well as the mesa width (i.e., thespacing between adjacent trenches). However, both of these dimensionsare limited by constraints imposed by manufacturing equipment,structural requirements, alignment tolerances, and transistoroperational requirements. For example, the minimum width of the mesaregion between adjacent trenches is limited by the space required forforming source and heavy body regions. Alignment tolerances associatedwith forming the trenches and the source and heavy body regions furtherlimit cell pitch reduction.

Many techniques for reducing the cell pitch of trench FETs have beenproposed, but none have been able to achieve a substantial reduction incell pitch without significantly complicating the manufacturing processor adversely impacting transistor performance.

Thus, there is a need for a technique whereby the cell pitch of trenchFETs can be reduced while maintaining a simple manufacturing process andsuperior transistor performance.

SUMMARY

In accordance with an embodiment of the invention, a semiconductorstructure comprises trenches extending into a semiconductor region.Portions of the semiconductor region extend between adjacent trenches toform mesa regions. A gate electrode is in each trench. Well regions of afirst conductivity type extend in the semiconductor region betweenadjacent trenches. Source regions of a second conductivity type are inthe well regions, and heavy body regions of the first conductivity typeare in the well regions. The source regions and the heavy body regionsare adjacent trench sidewalls, and the heavy body regions extend overthe source regions along the trench sidewalls to a top surface of themesa regions.

In one embodiment, the semiconductor structure further comprises aconductor extending into the trenches to contact the source regionsalong the trench sidewalls.

In another embodiment, the semiconductor structure further comprises aninterconnect layer extending over the semiconductor region andcontacting the heavy body regions along the top surface of the mesaregions.

In yet another embodiment, the source regions have portions extendinginto each trench.

In accordance with another embodiment of the invention, a trench fieldeffect transistor (FET) is formed as follows. Trenches are formedextending into a semiconductor region. Well regions of a firstconductivity type are formed in the semiconductor region. Heavy bodyregions of the first conductivity type are formed in the well regions.The heavy body regions have a higher doping concentration than the wellregions, and the heavy body regions abut the trench sidewalls. Sourceregions of a second conductivity type are formed in the well regionsalong the trench sidewalls directly below the heavy body regions. A gateelectrode is formed in each trench over the dielectric

In one embodiment, the source regions overlap the gate electrode alongthe trench sidewalls.

In another embodiment, the heavy body regions include verticallyextending portions that are separated from the trenches by the sourceregions.

In another embodiment, before the gate electrode is formed, a shieldelectrode is formed in a bottom portion of each trench, and aninter-electrode dielectric is formed over the shield electrode.

In yet another embodiment, a dielectric layer is formed in each trenchover the gate electrode, and a conductor is formed in each trench overthe dielectric layer. The conductor contacts the source regions alongthe trench sidewalls.

The following detailed description and the accompanying drawings providea better understanding of the nature and advantages of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1I are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions under the heavy body regions, according to an embodiment of theinvention;

FIG. 2 is a simplified cross-sectional view of a trench-gate FETstructure with source regions under the heavy body regions, according toan embodiment of the invention;

FIGS. 3A-3D are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions formed inside the trenches, according to another embodiment ofthe invention;

FIG. 4 is a simplified cross-sectional view of a trench-gate FETstructure with source regions formed inside the trenches, according toanother embodiment of the invention;

FIGS. 5A-L are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions formed under the heavy body regions and inside the trenches,according to an embodiment of the invention;

FIG. 6 is a simplified cross-sectional view of a trench-gate FETstructure with source regions formed under the heavy body regions andinside the trenches, according to an embodiment of the invention; and

FIG. 7 is a simplified cross-sectional view of a shielded gate trenchFET structure with source regions inside the trenches, according to yetanother embodiment of the invention.

DETAILED DESCRIPTION

In accordance with embodiments of the present invention, trench FETstructures with reduced cell pitch are obtained using simplemanufacturing processes. Some embodiments include FET structures withsource regions under the heavy body regions. Other embodiments includeFET structures with a source region inside the trench. Each of theseembodiments allows cell pitch to be reduced by moving the source regionsaway from the surface of the mesa regions, thus allowing a smallerminimum width of the mesa regions. These and other embodiments of theinvention as well as other features and advantages are described in moredetail below.

It should be understood that the following description is exemplaryonly, and the scope of the invention is not limited to these specificexamples. Note that the dimensions in the figures of this applicationare not to scale, and at times the relative dimensions are exaggeratedor reduced in size to more clearly show various structural features.Additionally, while only one trench is shown in each figure, it is to beunderstood that the structure illustrated may be replicated many timesin a semiconductor device.

FIGS. 1A-1I are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions under the heavy body regions, according to an embodiment of theinvention. In FIG. 1A, trench 101 is formed in semiconductor region 100using conventional photolithography and etch techniques. In oneembodiment, semiconductor region 100 includes n-type drift region 104extending over highly doped n+ type substrate 102. In some embodiments,trench 101 extends into and terminates within drift region 104. In otherembodiments, trench 101 extends through drift region 104 and terminateswithin substrate 102.

Shield dielectric 108, shield electrode 106, inter-electrode dielectric(IED) 110, gate dielectric 114, and gate electrode 112 are formed intrench 101 using known techniques. For example, formation of shielddielectric 108 and shield electrode 106 may include forming a dielectriclayer along the sidewalls and bottom of trench 101 using a conventionaldeposition or thermal oxidation process. A layer of polysilicon may beformed over the dielectric layer using a conventional polysilicondeposition process. The dielectric and polysilicon layers may then beetched using known techniques to recess the layers and form shielddielectric 108 and shield electrode 106 in the bottom portion of trench101. The formation of IED 110 may include forming a dielectric layerover shield electrode 106 using a conventional dielectric depositionprocess. One or more conventional dry or wet etch processes may then beused to recess the dielectric and form IED 110. Gate dielectric 114 maybe formed along the upper trench sidewalls and over the mesa regionsusing a conventional deposition or thermal oxidation process. Theformation of gate electrode 112 may include forming a polysilicon layerover gate dielectric 114 using a conventional polysilicon depositionprocess. One or more conventional polysilicon etch or chemicalmechanical polishing (CMP) processes may be used to remove thepolysilicon from over the mesa regions and form gate electrode 112.

In one embodiment gate electrode 112 may be doped n-type using knowntechniques. For example, in some embodiments, gate electrode 112 may bedoped in situ during the deposition process. In other embodiments, gateelectrode 112 may be doped after the deposition process by depositing adoped material over gate electrode 112 and thermally diffusing thedopants into gate electrode 112.

FIGS. 1B-1D illustrate one method of forming well regions 116 and heavybody regions 118 in semiconductor region 100. In other embodiments, wellregions 116 and heavy body regions 118 may be formed prior to trenchformation using known techniques.

In FIG. 1B, conventional implant processes may be used to implant p-typedopants into an upper portion of semiconductor region 100. In oneembodiment, the p-type well implant and the p+ heavy body implant may beblanket implants in the active area. In other embodiments, a mask may beused during the p+ heavy body implant to form periodic heavy bodyregions.

In FIG. 1C, one or more conventional etch processes may be used torecess gate electrode 112 in trench 101. In some embodiments, gateelectrode 112 may be recessed prior to the p-type well implant. In otherembodiments, heavy body regions 118 are relatively shallow to minimizeout-diffusion of the p-type dopants from heavy body regions 118 tounderlying source regions 124 that are formed in subsequent steps. Ingeneral, the depth and doping concentration of heavy body regions 118and the depth to which polysilicon 112 is recessed may be carefullycontrolled to obtain the desired structural features and deviceperformance.

In FIG. 1D, one or more conventional diffusion processes may be used toactivate the p-type dopants and form well regions 116 and heavy bodyregions 118 adjacent to trench 101. In one embodiment, a thermaldiffusion process may be used. The thermal diffusion process may drivethe p-type dopants into semiconductor region 100, and also formdielectric 120 over gate electrode 112 and dielectric 122 along uppertrench sidewalls and over mesa surfaces. In some embodiments, dielectric122 may include a portion of gate dielectric 114 and thus be thickerthan dielectric 120. In some embodiments, dielectrics 120, 122 may beremoved following the formation of well regions 116 and heavy bodyregions 118.

In FIG. 1E, n+ type source regions 124 may be formed under heavy bodyregions 118 flanking each side of trench 101 using known techniques. Inone embodiment, source regions 124 may be formed using one or moreconventional angled implant processes at angles of between about 20° to80°. In some embodiments, source regions 124 may be self aligned andthus formed using a blanket implant in the active area. For example, thebottom of source regions 124 along the sidewalls of trench 101 maydepend on the position of the upper surface of gate electrode 112. Thetop of source regions 124 along the sidewalls of trench 101 may dependon the depth of heavy body regions 118. Heavy body regions 118 may havea high doping concentration and remain p+ conductivity type even thoughn-type dopants are implanted into heavy body regions 118 during theformation of source regions 124. For example, in one embodiment heavybody regions 118 may be formed using a shallow boron or BF₂ implant at adose of between about 6×10¹⁵-8×10¹⁵ atoms/cm² and an energy of betweenabout 20-100 keV, and source regions 124 may be formed using a shallowarsenic implant at a dose of between about 3×10¹⁵-5×10¹⁵ atoms/cm² andan energy of between about 20-100 keV. When the source implant iscarried out before the heavy body implant, this implant sequence may bereversed.

As shown in FIG. 1F, some embodiments may include p+ regions 126 formedadjacent to source regions 124 using known techniques. The dose andenergy of p+ regions 126 can be carefully designed in accordance withknown techniques to advantageously reduce series resistance. Forexample, in one embodiment p+ regions 126 may be formed using one ormore conventional angled implant processes at angles of between about 7°to 80° to implant boron at a dose of between about 1×10¹⁴-1×10¹⁵atoms/cm² and an energy of between about 20-250 keV.

In FIG. 1G, dielectric material 128 may be deposited in the upperportion of trench 101 using known techniques. In one embodiment, aconventional chemical vapor deposition (CVD) process may be used to filltrench 101 with a dielectric material comprising oxide, such asborophosphosilicate glass (BPSG). In FIG. 1H, one or more conventionalwet or dry etch processes are used to recess dielectric material 128 intrench 101 to form dielectric layer 129. In some embodiments, portionsof source regions 124 are exposed along the trench sidewalls followingthe recess etch.

In FIG. 1I, the upper portion of trench 101 may be filled withinterconnect layer 130 using known techniques. In one embodiment,interconnect layer 130 may comprise metal and be formed using aconventional metal deposition process. Interconnect layer 130 contactssource regions 124 and heavy body regions 118 along the sidewalls oftrench 101, but is isolated from gate electrode 112 by dielectric layer129. In some embodiments, interconnect layer 130 may contact heavy bodyregions 118 along the mesa surfaces.

FIG. 2 is a simplified cross-sectional view of a trench-gate FETstructure with source regions 224 under heavy body regions 218,according to an embodiment of the invention. The trench-gate FETstructure shown in FIG. 2 may be formed in a manner similar to thatdescribed above with regard to FIGS. 1A-1I, excluding the formation ofshield dielectric 108, shield electrode 106, and IED 110. For example,trench 201 may be formed in semiconductor region 200 in a manner similarto that described above with regard to FIG. 1A except that trench 201may not extend as deep as trench 101 in FIG. 1A. In some embodiments,thick bottom dielectric (TBD) 215 may be formed along the bottom oftrench 201 to reduce gate-drain capacitance. Any one of a number ofknown process techniques for forming TBD may be used. For example, onemay use the process steps described in the commonly assigned patentapplication Ser. No. 12/143,510, titled “Structure and Method forForming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices,” filedJun. 20, 2008, which is incorporated herein by reference in itsentirety.

Gate dielectric 214 and gate electrode 212 may be formed in a mannersimilar to that described above with regard to FIG. 1A. Heavy bodyregions 218 and well regions 216 may be formed in a manner similar tothat described above with regard to FIGS. 1A-1D. Source regions 224, p+regions 226, dielectric layer 229, and interconnect layer 230 may beformed in a manner similar to that described above with regard to FIGS.1E-1I.

As can be seen in FIGS. 1I and 2, positioning source regions 124, 224under heavy body regions 118, 218 advantageously allows the cell pitchto be reduced. The cell pitch is not limited by the space required forforming the source regions along the surface of the mesa region or bythe associated alignment tolerances. In some embodiments, the cell pitchcan be reduced by about 25-50% compared to conventional trench FETstructures. Also, the trench FET structures illustrated in these figurescan be formed using simple manufacturing processes. For example, thesource contact is self-aligned, and thus a mask step can be eliminated;the heavy body and well can be annealed at the same time, and thus aseparate heavy body anneal can be eliminated; and interconnect layer130, 230 contacts the heavy body regions along the trench sidewalls andmesa surfaces, and thus formation of heavy body contact openings whichtypically requires a masking step can be eliminated. Other advantagesand features enjoyed by trench FETs formed according to embodiments ofthe present invention include increased yield (using self-alignedprocess improves alignment of source and heavy body contacts), lowersource contact resistance (no heavy body implant through sourcecontacts; no auto-doping of source contacts from BPSG during heavy bodyanneal), improved heavy body contact (by contacting the very uniform p++doped mesa surfaces as well as contacting the heavy body regions alongthe upper trench sidewalls), scaling of the heavy body contact (due toimproved heavy body contact), lower channel resistance, improvedthreshold voltage and higher breakdown voltage (less diffusion fromheavy body region into the channel).

FIGS. 3A-3D are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions formed inside the trenches, according to another embodiment ofthe invention. This embodiment may include a conductive material insidethe trench serving as part, or all, of the source region, and aninterconnect layer covering the structure and contacting the conductivematerial as shown in FIG. 3D.

The structure illustrated in FIG. 3A may be formed in a manner similarto that described above with regard to FIGS. 1A-1H and thus are notdescribed here in detail. In FIG. 3B, dielectric spacers 332 are formedalong the exposed upper sidewalls of trench 301 using known techniques.In one embodiment, spacers 332 comprise nitride and are formed usingconventional nitride CVD and spacer etch processes. In some embodiments,a dielectric layer (not shown) may be formed along the upper trenchsidewalls prior to the formation of spacers 332 to buffer the stress ofspacers 332.

In FIG. 3C, dielectric layer 334 may be formed over the mesa regionsadjacent to each trench 301. Spacers 332 prevent formation of adielectric layer along upper trench sidewalls during this step. In oneembodiment, dielectric layer 334 may comprise oxide and be formed usinga conventional thermal oxidation process at a temperature of between800-1000° C. The low-temperature may minimize dopant out-diffusion fromwell regions 316 and heavy body regions 318. The oxidation process mayincrease the thickness of dielectric layer 329 over gate electrode 312.This can be compensated for during the recess etch corresponding to theprocess step illustrated by FIG. 1H. Following formation of dielectriclayer 334, spacers 332 may be removed to expose upper trench sidewalls.In one embodiment, spacers 332 are removed using a conventional hotphosphoric acid etch.

In FIG. 3D, conductive material 336 may be formed in trench 301 usingknown techniques. In one embodiment, conductive material 336 comprisespolysilicon and may be deposited using a conventional polysilicondeposition process. The polysilicon may be doped e.g., n-type, usingknown techniques. For example, in one embodiment the polysilicon isdoped in situ using a conventional in situ deposition process. One ormore conventional etch and/or CMP processes (e.g., using dielectric 334as an etch stop) may be used to remove the portions of the polysiliconextending outside trench 301. In some embodiments, the polysilicon maybe slightly recessed into trench 301. Dielectric layer 334 may protectthe mesa surfaces during the polysilicon removal process. Dielectriclayer 334 may be removed using conventional etch and/or CMP processes.In other embodiments, conductive material 336 may comprise silicon andbe formed using a conventional selective epitaxial deposition process.In some embodiments, conductive material 336 may be doped in situ withn-type dopants, such as phosphorus and/or arsenic.

Interconnect layer 338 may be formed over the structure using knowntechniques. In one embodiment, interconnect layer 338 may comprise metaland be formed using conventional metal deposition processes.Interconnect layer 338 may contact heavy body regions 318 along the mesasurfaces as well as the top surface of conductive material 336. In oneembodiment, source regions 324 may be formed by out-diffusing dopants(e.g., phosphorous) from conductive material 336 into well regions 314using known techniques, rather than by the angled source implant asshown in FIG. 1E.

FIG. 4 is a simplified cross-sectional view of a trench-gate FETstructure with source regions formed inside the trenches, according toanother embodiment of the invention. Trench 401, TBD 415, gatedielectric 414, and gate electrode 412, may be formed in a mannersimilar to that described above with regard to FIG. 2. Source regions424, p+ regions 426, and dielectric layer 429 may be formed in a mannersimilar to that described above with regard to FIGS. 3A-3D. Theremaining portions of the trench-gate FET structure illustrated in FIG.4 may also be formed in a manner similar to that described above withregard to FIGS. 3A-3D.

FIGS. 5A-5L are simplified cross-sectional views at various stages of aprocess for forming a shielded gate trench FET structure with sourceregions formed inside the trenches and under the heavy body regions,according to an embodiment of the invention. FIGS. 5A-5D correspond topreviously described FIGS. 1A-1D and thus are not described here indetail.

In FIG. 5E, dielectric spacers 532 may be formed along the verticalsidewalls of dielectric 522 using known techniques. In one embodiment,spacers 532 may comprise nitride and be formed using conventionalnitride CVD and spacer etch processes.

In FIG. 5F, dielectric layer 536 may be formed over the mesa regionsadjacent to trench 501, and dielectric layer 538 may be formed over gateelectrode 512. In some embodiments, dielectric layers 536, 538 mayinclude portions of dielectric layers 522, 520, respectively. Dielectricspacers 532 protect the portions of dielectric layer 522 extending alongupper trench sidewalls during the dielectric formation process. In oneembodiment, dielectric layers 536, 538 may comprise oxide and be formedusing a conventional thermal oxidation process at a temperature ofbetween 700-800° C. The low-temperature process may minimize dopantout-diffusion from well regions 516 and heavy body regions 518. Spacers532 prevent oxidation of the mesa along the upper trench sidewallsduring the thermal oxidation. Following formation of dielectric layers536, 538, spacers 532 may be removed using one or more conventional etchprocesses. In one embodiment, spacers 532 may be removed using a hotphosphoric acid etch.

In FIG. 5G, fill material 540 may be formed in an upper portion oftrench 501 and over the mesa regions adjacent to trench 501. In oneembodiment, fill material 540 comprises polysilicon and may be formedusing a conventional polysilicon deposition process. In FIG. 5H, thepolysilicon may be recessed in trench 501 using one or more conventionalwet or dry etch processes to form sacrificial layer 541. In oneembodiment, the upper surface of sacrificial layer 541 may be lower intrench 501 than the bottom surface of heavy body regions 518 for reasonsthat will become evident from subsequent steps. Dielectric layers 522and 536 protect the silicon mesa during the polysilicon recess.

In FIG. 5I, dielectric spacers 542 may be formed along the exposedvertical sidewalls of dielectric layer 522 using known techniques. Inone embodiment, spacers 542 may comprise oxide and be formed usingconventional oxide deposition and spacer etch processes.

In FIG. 5J, sacrificial layer 541 may be removed using known techniques.In one embodiment, sacrificial layer 541 may be removed using one ormore conventional dry isotropic etch and/or wet etch processes. The etchprocesses may be selective to sacrificial layer 541 so that minimalamounts of spacers 542 and dielectric layers 536, 538 are removed.

The exposed portions of dielectric layer 522 adjacent to sacrificiallayer 541 may also be removed to expose small windows 521, through whichwell regions 616 can be accessed. In one embodiment, dielectric layer522 may comprise oxide, and windows 521 may be formed by removing theexposed portions of dielectric layer 522 using one or more conventionalwet etch processes. At least a portion of spacers 542 and dielectriclayers 536, 538 may also be removed. For example, in some embodimentsspacers 542 may be completely removed as shown in FIG. 5J. In otherembodiments, at least portions of spacers 542 remain. The loss ofthickness of dielectric layer 538 can be compensated for when it isfirst formed to ensure sufficient insulation between gate electrode 512and source region 544 formed next. Higher voltage devices may require athicker dielectric layer 538 than lower voltage devices.

In FIG. 5K, n+ type source region 544 may be formed over dielectriclayer 538 using known techniques. Source region 544 contacts the exposedportion of semiconductor region 500 along the sidewalls of trench 501.In one embodiment, source region 544 may comprise polysilicon and beformed using a conventional low-temperature selective CVD depositionprocess at a temperature of between 500-650° C. In other embodiments,source region 544 may comprise silicon and be formed using aconventional selective epitaxial deposition process. In someembodiments, source region 544 may be doped in situ with n-type dopants,such as phosphorus and/or arsenic.

At least a portion of the n-type dopants in source region 544 maydiffuse into well regions 516 to form laterally extending portions 546of source region 544. In one embodiment, n-type dopants may diffuse intowell regions 516 during the deposition of source region 544. In otherembodiments, a conventional diffusion process may be used to diffusen-type dopants from source region 544 into well regions 516. In someembodiments, laterally extending portions 546 may overlap gate electrode512 along a depth of the trench. The extent of diffusion into wellregions 516 can be carefully designed to reduce series resistance. Forexample, if more out-diffusion is desired, source region 544 may bedoped with phosphorous dopants, and where minimal out-diffusion isdesired, source region 544 may be doped with arsenic dopants.

In FIG. 5L, dielectric layer 536 may be removed using conventional etchand/or CMP processes, and the upper portion of trench 501 may be filledwith interconnect layer 548 using known techniques. In one embodiment,interconnect layer 548 may comprise metal and be formed using aconventional metal deposition process. Interconnect layer 548 maycontact the top surface of source region 544 inside trench 501 and maycontact heavy body regions 518 along the surface of the mesa regions. Inanother embodiment, dielectric layer 522 may also be removed beforeforming interconnect layer 548 so that interconnect layer 548 makesadditional contact to heavy body regions 518 along the upper trenchsidewalls.

FIG. 6 is a simplified cross-sectional view of a trench-gate FETstructure with source regions formed inside the trenches and under theheavy body regions, according to an embodiment of the invention. Trench601, TBD 615, gate dielectric 614, and gate electrode 612 may be formedin a manner similar to that described above with regard to FIG. 2.Source regions 624 and p+ regions 626 may be formed in a manner similarto that described above with regard to FIGS. 1E-1F. The remainingportions of the trench-gate FET structure illustrated in FIG. 6 may beformed in a manner similar to that described above with regard to FIGS.5E-5L.

FIG. 7 is a simplified cross-sectional view of a shielded gate trenchFET structure with source regions formed inside the trenches, accordingto yet another embodiment of the invention. The shielded gate trench FETstructure shown in FIG. 7 may be formed in a manner similar to thatdescribed above with regard to FIGS. 5A-5L, excluding the formation oflaterally extending portions 546. For example, in one embodiment, n-typesource region 744 may be doped in situ with arsenic, and due to the lowdiffusivity of arsenic, very little arsenic may diffuse into wellregions 716 during the deposition of source region 744. In anotherembodiment, prior to forming the interconnect layer 748, a conductivematerial (not shown) may be formed in the upper portion of trench 701 ina manner similar to that described above with regard to FIG. 3D.Alternatively, a trench-gate FET variation of FIG. 7 may be formed in amanner similar to that described above with regard to FIG. 6.

The trench FET structures shown in FIGS. 5L, 6, and 7 advantageouslyprovide many of the same advantages and features as the structures shownin FIGS. 1I, 2, 3D, and 4 described above. Additionally, the trench FETstructures shown in FIGS. 5L and 6 may provide overlap between thelaterally extending regions 546, 646 and the gate electrode 512, 612along a depth of the trench thus reducing parasitic transistor effects.Laterally extending regions 546, 646 may also reduce series resistance.The trench FET structure shown in FIG. 7 may provide a structure with nodirect contact between the source and heavy body regions, thus reducinginter-diffusion between the heavy body and source regions.

Note that while the embodiments depicted by FIGS. 1I, 2, 3D, 4, 5L, 6,and 7 show n-channel FETs, p-channel FETs may be obtained by reversingthe polarity of the various semiconductor regions. Further, in theembodiment where regions 104, 204, 304, 404, 504, 604, 704 are epitaxiallayers extending over substrate 102, 202, 302, 402, 502, 602, 702,respectively, MOSFETs are obtained where the substrate and epitaxiallayer are of the same conductivity type, and IGBTs are obtained wherethe substrate has the opposite conductivity type to that of theepitaxial layer.

Although a number of specific embodiments are shown and described above,embodiments of the invention are not limited thereto. For example, it isunderstood that the doping polarities of the structures shown anddescribed could be reversed and/or the doping concentrations of thevarious elements could be altered without departing from the invention.Also, the various embodiments described above may be implemented insilicon, silicon carbide, gallium arsenide, gallium nitride, diamond, orother semiconductor materials. Further, the features of one or moreembodiments of the invention may be combined with one or more featuresof other embodiments of the invention without departing from the scopeof the invention.

Therefore, the scope of the present invention should be determined notwith reference to the above description but should be determined withreference to the appended claims, along with their full scope ofequivalents.

1. A semiconductor structure comprising: trenches extending into asemiconductor region, portions of the semiconductor region extendingbetween adjacent trenches forming mesa regions; a gate electrode in eachtrench; well regions of a first conductivity type extending in thesemiconductor region between adjacent trenches; source regions of asecond conductivity type in the well regions; and heavy body regions ofthe first conductivity type in the well regions, wherein the sourceregions and the heavy body regions are adjacent trench sidewalls, andthe heavy body regions extend over the source regions along the trenchsidewalls and to a top surface of the mesa regions.
 2. The semiconductorstructure of claim 1 further comprising: a conductor extending into thetrenches to contact the source regions along the trench sidewalls. 3.The semiconductor structure of claim 1 further comprising: aninterconnect layer extending over the semiconductor region andcontacting the heavy body regions along the top surface of the mesaregions.
 4. The semiconductor structure of claim 1 wherein the sourceregions have portions extending into each trench.
 5. The semiconductorstructure of claim 4 further comprising: an interconnect layer extendingin each trench to contact the portions of the source regions extendinginto each trench, the interconnect layer further contacting the heavybody regions along the top surface of the mesa regions.
 6. A trenchfield effect transistor (FET) comprising: trenches extending into asemiconductor region; well regions of a first conductivity typeextending in the semiconductor region between adjacent trenches; heavybody regions of the first conductivity type extending over the wellregions and abutting sidewalls of adjacent trenches, wherein a dopingconcentration of the heavy body regions is greater than a dopingconcentration of the well regions; source regions of a secondconductivity type abutting the trench sidewalls, the source region beingembedded in the well regions below at least a portion of the heavy bodyregions; and a gate electrode in each trench, the gate electrode beinginsulated from the well regions, the heavy body regions, and the sourceregions by a dielectric.
 7. The trench FET of claim 6 wherein the sourceregions overlap the gate electrode along the trench sidewalls.
 8. Thetrench FET of claim 6 wherein the heavy body regions include verticallyextending portions that are separated from the trenches by the sourceregions.
 9. The trench FET of claim 6 further comprising: a shieldelectrode in each trench under the gate electrode; and aninter-electrode dielectric extending between the shield electrode andthe gate electrode.
 10. The trench FET of claim 6 further comprising: asilicon region in each trench over the gate electrode, wherein thesilicon region is isolated from the gate electrode by a dielectriclayer, and wherein the silicon region contacts the source regions alongthe trench sidewalls; and an interconnect layer extending over thesemiconductor region and contacting the silicon regions and the heavybody regions.
 11. The trench FET of claim 6 further comprising: a sourcecontact in an upper portion of each trench contacting the source regionsand the heavy body regions along the trench sidewalls.
 12. The trenchFET of claim 6 wherein the source regions have portions extending intoeach trench, and the portions of the source regions extending into eachtrench extend over the gate electrode and are insulated from the gateelectrode by a dielectric layer.
 13. The trench FET of claim 12 furthercomprising: an interconnect layer extending in each trench, wherein theinterconnect layer contacts the portions of the source regions extendinginto each trench.
 14. A trench field effect transistor (FET) comprising:trenches extending into a semiconductor region; a gate electroderecessed in each trench; a dielectric extending over the gate electrode;a source region of a first conductivity type recessed in each trenchover the dielectric; and a source interconnect extending into eachtrench to contact an upper surface of the source region.
 15. The trenchFET of claim 14 wherein all source contacts are in the trenches.
 16. Thetrench FET of claim 14 further comprising: a shield electrode in eachtrench under the gate electrode; and an inter-electrode dielectricextending between the shield electrode and the gate electrode.
 17. Thetrench FET of claim 14 further comprising: well regions of a secondconductivity type abutting adjacent trenches, wherein each source regionincludes portions extending laterally into the well regions; and heavybody regions of the second conductivity type extending directly over thewell regions and the laterally extending portions of the source regions,the heavy body regions having a higher doping concentration than thewell regions, the laterally extending portions of the source regionoverlap the gate electrode along trench sidewalls.
 18. The trench FET ofclaim 14 further comprising: well regions of a second conductivity typeabutting adjacent trenches; and heavy body regions of the secondconductivity type extending over the well regions and abutting uppersidewalls of each trench, wherein a doping concentration of the heavybody regions is greater than a doping concentration of the well regions.19. The trench FET of claim 18 wherein the source region is configuredso that no portion of the source region abuts any part of the heavy bodyregions.
 20. The trench FET of claim 18 wherein the heavy body regionsextend along upper surfaces of mesa regions adjacent each trench, andthe source interconnect contacts the heavy body regions along the uppersurfaces of the mesa regions but is insulated from the heavy bodyregions along the trench sidewalls.